1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device, and specifically to a manufacturing method of a semiconductor device as a solid-state image sensing device formed by arranging pixels having photodiodes in a matrix on a light receiving surface thereof.
2. Background Art
A semiconductor device is generally formed on a semiconductor substrate. In the past, its performance has been remarkably improved with the progress of the microfabrication technology of lithography. However, the process cost of the lithography fabrication technology is increased as the fabrication becomes finer.
For example, as the exposure wavelength of exposure equipment becomes shorter to a g-ray (436 nm), an i-ray (365 nm), a Kr—F laser (248 nm), and an Ar—F laser (193 nm), the device price is increased and the photoresist material price becomes higher.
Further, technological problems are increased in improvements of performance of the semiconductor device by microfabrication and improvements of characteristics may be physically difficult.
For example, in the solid-state image sensing device, a photoelectric conversion element should be reduced as microfabrication makes progress. In this case, reduction of the saturated amount of charge and measures for random noise are necessary.
In the circumstances, a manufacturing method of a semiconductor device using a bonding technology of a semiconductor substrate attracts attention.
As an example of the manufacturing method, there is a method of fabricating a semiconductor device by bonding a substrate having a semiconductor function and a support substrate, and then, further performing a working process thereon.
For example, JP-A-4-364070 discloses a manufacturing method of an SRAM (Static Random Access Memory).
A manufacturing method of a semiconductor device using a bonding technology of substrates according to the above described related art will be described with reference to FIGS. 29A to 29D and FIGS. 30A to 30D.
Here, a semiconductor substrate 110 having semiconductor elements thereon and a support substrate 140 are bonded.
First, as shown in FIG. 29A, formation of plural transistors and formation of upper layer wires are performed on the first surface S1 of the semiconductor substrate 110 using a typical semiconductor manufacturing process.
FIG. 29B is an enlarged view of a part X of FIG. 29A. For example, element isolation insulator films 111 are formed in the semiconductor substrate 110, and the transistors are formed by forming gate electrodes 120 via gate insulator films (not shown), and an insulator film 121 is formed in the upper layer thereof. Here, upper layer wires 122 containing contacts are embedded in the insulator film.
Then, as shown in FIG. 29C, an adhesive layer 130 is applied onto the first surface S1 of the semiconductor substrate 110.
Then, as shown in FIG. 29D, the support substrate 140 is bonded to the first surface S1 of the semiconductor substrate 110 by the adhesive layer 130.
In this regard, for example, the substrates are bonded using notches (or orientation flats) as a characteristic shape of the semiconductor substrate.
Then, heating treatment is performed for the purpose of an improvement of adhesion between the semiconductor substrate 110 and the support substrate 140.
FIG. 30A shows FIG. 29D vertically reversed.
Then, as shown in FIG. 30B, the semiconductor substrate 110 is ground from the rear surface and the semiconductor substrate 110 is finally made thinner to have a predetermined film thickness by wet-etching processing.
Then, as shown in FIG. 30C, functional layers 115 are formed on the second surface S2 of the semiconductor substrate 110 obtained in the above described manner.
FIG. 30D is an enlarged view of a part Y of FIG. 30C. Films as the functional layers 115 are formed on the second surface S2 of the semiconductor substrate 110 bonded to the support substrate 140 in the above described manner. Then, a resist mask of a processing pattern is formed by applying a photoresist film, and performing overlay exposure on the circuit pattern of the semiconductor substrate 110, PEB (Post Exposure Bake), and developing treatment. Using this as a mask, processing treatment such as etching is performed, and thereby, the functional layers 115 having a desired function are formed.
Here, not only the method using the adhesive layer as a material for bonding, but also a method of forming oxide film materials on both the semiconductor substrate and the support substrate and bonding the semiconductor substrate and the support substrate by heating them is known. Further, the method of bonding the semiconductor substrate and the support substrate may be any method.
The overlay exposure on the circuit pattern of the above described semiconductor substrate is realized using an alignment optical system of the exposure equipment of detecting positions of rough alignment marks and fine alignment marks formed on the semiconductor substrate.
A typical process of performing overlay exposure of the exposure equipment is performed in the following manner, for example.
First, the mask is placed on a reticle stage, the equipment condition and the reference position of the mask are set, and the semiconductor substrate is placed on a wafer stage.
Then, for example, as alignment measurement of the exposure equipment, first, the rough alignment marks formed on the scribe lines of respective shots are measured and the shot arrangement of the entire semiconductor substrate is calculated.
The fine alignment marks formed on the scribe lines of respective shots are measured, and offsets X, Y of the entire wafer, the wafer scaling X, Y, wafer rotation, and orthogonality are calculated. Thereby, the detailed shot arrangement is determined. Furthermore, three or more alignment marks formed at exposure of respective shots on the scribe lines are measured, and thereby, also the shot scaling factor, the shot orthogonality, and the shot rotation can be calculated.
Then, settings necessary for exposure are made, and mask patterns are sequentially transferred onto the semiconductor substrate.
Then, the presence or absence of the semiconductor substrate to be exposed to light is determined and, if it is present, the wafer is unloaded and a new substrate is placed on the wafer stage, and the same process as that described above is repeated.
The manufacturing method of a semiconductor substrate using bonded substrates is described in JP-A-4-364070. JP-A-4-364070 discloses a method of forming an SRAM as a high-resistive device using bonded substrates. The variations in the resistance value of the high-resistive SRAM are suppressed and the interference noise is prevented. Further, independent of the memory cell area, the resistive device having a desired resistive length can be formed. Thereby, higher integration and higher capacity can be realized.
Further, a manufacturing method of a semiconductor device using bonded substrates is disclosed in JP-A-4-259249. In JP-A-4-259249, an N-channel MOS transistor (hereinafter, also referred to as NMOS) is formed as a TFT (thin-film transistor), and then, bonding is performed and a P-channel MOS transistor (hereinafter, also referred to as PMOS) is formed as a TFT on the opposed surface. The device has an SOI (Silicon on Insulator) structure in which the TFTs are formed on both sides of an insulator layer.
In the manufacturing method, a first alignment mark and a second alignment mark are provided, and the first alignment mark is used when the NMOSTFT is formed and the second alignment mark is used when the PMOSTFT is formed on the opposed surface.
Here, the semiconductor material as an active region is 800 nm or less and silicon oxide is used as the insulator layer of the SOI substrate, and thus, alignment light can be transmitted through the SOI substrate. Thereby, pattern formation can be performed using the second alignment mark provided on the NMOS formation surface when the PMOS is formed.
The bonding of the semiconductor substrate and the support substrate is performed according to a mechanical method using substrate outer shapes. FIGS. 31A and 31B are a plan view and a perspective view showing the process. An adhesive layer is attached to a surface of one of a semiconductor substrate W1 on which semiconductor chips CP pattern is provided and a support substrate W2, and then, the outer shapes including notches (N1, N2) are aligned and the substrates are bonded. Then, heat treatment for improving the adhesion between the substrates is performed.
However, recently, for higher added value of the semiconductor device, processing of a silicon layer thicker than 800 nm has been necessary.
For example, transistors are formed on one surface of a semiconductor layer thicker than 800 nm and elements having other functions are formed and functional layers are processed on the other surface.
In the above description, when a pattern is exposed on the second surface according to the circuit pattern of the first surface, the alignment marks provided on the first surface are detected from the second surface side. Here, visible light is used as an alignment light source of exposure equipment, and thus, if the silicon layer of the semiconductor material becomes thicker than 800 nm, the intensity of detection light of the alignment marks from the second surface side is drastically attenuated or may be impossible to be detected.
FIGS. 32A and 32B show schematic views of an example of alignment marks used in exposure equipment. These marks are rough alignment marks having asymmetric configurations, Y-marks YM and X-marks XM.
The marks include marks of three lines of sequentially arranged square patterns, and distances of the groups of patterns are 26 μm and 20 μm, respectively.
The positions of the marks are detected by the reflected light obtained when alignment light is applied. For example, an He—Ne laser is relatively scanned in scanning directions (SC1, SC2) in semi-transmissive orange directions. Alternatively, mark detection is performed by image recognition by the visible light. In this regard, signals along the three rows and noise due to scattered light from edges of scribe lines and chip patterns are detected. From the detection signals, the marks detected at the distances of 26 μm and 20 μm from the upstream of the scanning in detection of the Y-marks YM and detected at the distances of 20 μm and 26 μm from the upstream of the scanning in detection of the X-marks XM are recognized as rough alignment marks.
Then, using the rough alignment marks, the rough alignment marks after bonding have shapes shown in FIGS. 32C and 32D. In this case, the Y-marks YM can be recognized to be horizontally reversed, and the X-marks XM have mark distances of 26 μm, 20 μm, respectively.
In this regard, by the scanning using the He—Ne laser, the X-marks XM are not recognizable. This is because the detection distances of the X-marks XM are set to 20 μm, 26 μm as alignment parameters within exposure equipment, and signals adapted thereto are not detected.
On the other hand, if the detection distances of the marks are input as 20 μm, 26 μm, respectively, the X-marks become recognizable, however, there are problems that setting these values at each time in the mass production line for a wide variety of products in small quantities is not practical with reduced efficiency.